1. Field of the Invention
The present invention relates mainly to a method of switching a PLL characteristic allowing to achieve a reduction in operational noise in a PLL circuit, and a PLL circuit.
2. Description of Related Art
FIG. 12 is a block diagram showing a configuration of a conventional art of a PLL circuit. FIG. 13 is a circuit diagram showing a configuration of a low pass filter, namely a loop filter, which is one of the components of the PLL circuit in FIG. 12. FIG. 14 is a timing chart showing operation of the PLL circuit in FIG. 12.
According to this PLL circuit, as shown in FIG. 12, aphase difference between a divided signal 6 obtained by dividing an output signal 9 of a voltage controlled oscillator 1 into 1/M by a variable divider 2 and a reference signal 7 outputted from a temperature compensated crystal oscillator 11 is detected by a phase comparator 3. A voltage pulse with a pulse width according to the phase difference between the divided signal 6 and the reference signal 7, the phase difference having been detected by the phase comparator 3 is sent to charge pumps 4 and 10 from the phase comparator 3. The charge pumps 4 and 10 output a voltage or a current according to an output of the phase comparator 3. The charge pump 4 is directly connected to a loop filter 5. Meanwhile, the charge pump 10 is connected to the loop filter 5 via a switching element (SW1) 14 which is switched on or off according to a natural angular frequency switching signal 16. Accordingly, when the natural angular frequency switching signal 16 is in a first state, only the output of the charge pump 4 is supplied to the loop filter 5. Meanwhile, when the natural angular frequency switching signal 16 is in a second state, both of the outputs of the charge pumps 4 and 10 are supplied to the loop filter 5. The outputs of these charge pumps 4 and 10 are smoothed by the loop filter 5, and transmitted to the voltage controlled oscillator 1 as a control voltage 13. In this case, a natural angular frequency ωn of the PLL circuit has different values according to the cases of supplying only the output of the charge pump 4 to the loop filter 5, and of supplying both outputs of the charge pumps 4 and 10 to the loop filter 5. In the later case, the natural angular frequency ωn becomes higher as compared with that in the former case.
The natural angular frequency switching signal 16 is inputted also into the loop filter 5, so that values of resistances composing the loop filter 5 are switched depending on a state of the natural angular frequency switching signal 16. It is intended that even when the natural angular frequency ωn is switched according to supplying or not supplying the output of the charge pumps 10 to the loop filter 5 as described above, a damping factor ζ of the PLL circuit may not be changed.
As shown in FIG. 13, the loop filter 5 includes a capacitive element Cp connected between an output terminal of the charge pump 4 and a ground, a series circuit of resistance elements Rz1 and Rz2 and a capacitive element Cz connected between the output terminal of the charge pump 4 and the ground, a switching element (SW2) 17 connected in parallel to the resistance element Rz2. The switching element (SW2) 17 is switched on or off depending on the state of the natural angular frequency switching signal 16. The output terminal of the charge pump 4 is connected to a control voltage terminal of the voltage controlled oscillator 1 as it is.
According to such a manner as described above, the output signal 9 of the voltage controlled oscillator 1 is divided into 1/M by the variable divider 2, and fed back to the phase comparator 3 as the divided signal 6. Accordingly, supposing that a frequency division ratio of the variable divider 2 is M, and a frequency of the reference signal 7 is fref, a frequency fo of the output signal 9 of the voltage controlled oscillator 1 is expressed by Equation (1).fo=M×fref  Equation (1)
Meanwhile, the natural angular frequency ωn and the damping factor ζ, which are typically given as a measure of a loop characteristic of the PLL circuit, is expressed by Equations (2) and (3).ωn=(K×ω2)1/2  Equation (2)ζ(=(½)×(K÷ω2)1/2  Equation (3)Where,                ω2=1/(Cz×Rz),        K=(Kvco×Icp×Rz)/(2π×M),        10×Cp<Cz,        
Icp is a sum of the output currents of the charge pumps 4 and 10 when the switching element (SW1) 14 is switched on, or is an output current of the only charge pump 4 when the switching element (SW1) 14 is switched off,
Kvco is a gain of the voltage controlled oscillator 1,
Rz is a sum of resistance values of the resistance elements Rz1 and Rz2 when the switching element (SW2) 17 is switched off, or a resistance value of only the resistance element Rz1 when the switching element (SW2) 17 is switched on.
Cz is a capacitance value of the capacitive element Cz.
Here, it is broadly known that an optimal damping factor ζ is approximately 0.7 due to a high-speed response of the PLL circuit.
According to this conventional art, however, in order to achieve both of the high-speed response and the high C/N ratio, the natural angular frequency ωn is switched when the frequency is pulled in and is in a steady state.
First, during a steady state, the natural angular frequency switching signal 16 stays in “L” level, so that the switching element (SW1) 14 is switched off, and a current supplied to the loop filter 5 is only the output current of the charge pump 4. Accordingly, the natural angular frequency ωn of the PLL circuit stays in a low state, and the PLL circuit is kept in a locked state.
Subsequently, when switching the frequency division ratio M of the variable divider 2, the natural angular frequency switching signal 16 rises to “H” level for a certain period from its moment. The switching element (SW1) 14 is switched on in response to this natural angular frequency switching signal 16. As a result, the current supplied to the loop filter 5 will be increased to the summed value of the output currents of the charge pumps 4 and 10 from the output current of only the charge pump 4. Thus, the natural angular frequency ωn is increased and frequency pulling operation is performed at high speed. At this time, the switching element (SW2) 17 is switched on. Thus, both ends of the resistance element Rz2 are short-circuited, and the damping factor ζ is adjusted to approximately 0.7 the same value as that during a steady state.
For example, when the value of the current Icp is set to four times, and the value of the resistance element Rz is set to one half only during a frequency pulling, the natural angular frequency ωn can be increased by two times, while keeping the damping factor ζ constant according to Equations (2) and (3). As a result, pulling of the frequency and the phase can be completed at high speed.
Subsequently, by setting the natural angular frequency switching signal 16 to “L” state, the switching elements (SW1, SW2) 14 and 17 are switched off, so that the natural angular frequency ωn is reduced to a steady state value, while keeping the value of the damping factor ζ constant, thereby making it possible to achieve the high C/N ratio.
A relationship between a change of the frequency fo of the output signal of the voltage controlled oscillator 1, and a change of the natural angular frequency switching signal 16 is shown in FIG. 14. In FIG. 14, the frequency fo is stable before time t1, and the PLL circuit stays in a locked state. A period from time t1 to time t2 is a frequency pulling period. A period from time t2 to time t3 is a phase pulling period. After time t3, the frequency fo is stable and the PLL circuit enters a locked state.
Non-patent document 1: “Substrate Injection and Crosstalk in CMOS Circuits” Bell Laboratories, Lucent Technologies IEEE1999 CUSTOM INTEGRATED CIRCUITS CONFERENCE
According to the configuration of the conventional art, however, as the drawback of switching the natural angular frequency ωn, the current supplied to the loop filter 5 is increased to the summed value of the output currents of the charge pumps 4 and 10 from the output current of only the charge pump 4 when the natural angular frequency switching signal 16 is in “H” level. As a result, an operating current of the PLL circuit is also increased, so that some currents flow into a semiconductor substrate, and interferes with other blocks, such as the transmission circuit and the reception circuit that are integrated with the PLL circuit on the same semiconductor substrate. Thus, various characteristics of the transmission and reception circuits are degraded. In other words, there has been a problem that the operational noise in the PLL circuit has been large.
The interference described above is produced in a following structure, for example.
FIG. 15 is a sectional view showing a vertical structure of two diodes separated by an insulator. In FIG. 15, reference numeral 101 represents a p− type Si substrate; reference numeral 102 and 103, p++ type regions formed on the p− type Si substrate 101; reference numerals 104 and 105, n+ type regions formed on the p++ type regions 102 and 103, respectively; reference numeral 106, an insulator for isolation embedded in the p− type Si substrate 101; reference numeral 107, a parasitic resistance formed between the p++ type regions 102 and 103; and reference numeral 108, a parasitic capacitance formed between p++ type regions 102 and 103. The interference described above is produced by such elements.